SPI timing and transfer rate.

Hello Everyone,

I am using SPI to sample output of an ADC which can be read at up to 20 Mbps.  I am trying to achieve the highest possible transfer rate but I am not able to do so.  SPI module is configured on r_sci_spi with RX and TX transfer drivers on r_dtc.  Currently, SPI bitrate is set to 1Mbps.  Interrupt priorities for the SPI module are set to 2.

SPI transactions are initiated in a GPT ISR running at 48 kHz.  GPT's interrupt priority is also set to 2.  Each sample size is 16 bits (spi_rx_value below).  In each call to the ISR, I enable CS (active low) and then begin the SPI transaction.  Code is pretty standard:

if (adc_transfer_done != true) {
    adc_premature_call_counter++;
    return;
}

adc_transfer_done = false;
g_ioport.p_api->pinWrite(cs_pin, IOPORT_LEVEL_LOW);
err = pSPI->p_api->read(pSPI->p_ctrl, &spi_rx_value, sizeof(spi_rx_value), SPI_BIT_WIDTH_8_BITS);
if (err == SSP_SUCCESS) {
    adc_good_transfer_counter++;
} else {
    adc_bad_transfer_counter++;
}

The SPI callback sets CS pin high and sets the adc_transfer_done flag to true at which point the transfer is complete.  Once the previous transfer is complete, GPT ISR begins a new one.  What I find is that, while adc_bad_transfer_counter always stays at 0, adc_premature_counter increments very fast.  Only a fraction of all calls to the GPT ISR are able to start the next transfer as most of the time, the previous transfer is not yet done.

When I time the whole transaction, from the moment CS is enabled to the moment it is disabled, it takes 47 usec.  Since the GPT is running at 48 kHz, it fires every 20.83 usec.  This means that SPI transactions do not have enough time to complete for each call to the GPT ISR.  The actual transfer of data, the time period during which CLK is toggling is 16 usec.  This is expected because the bitrate is 1Mbps and sample size is 16 bits.  However, a scope shows that it takes 19 usec from the time CS is enabled to the time when CLK begins to toggle.  Once CLK stops, it takes another 12 usec for the CS to be disabled.

Would anyone know why 19 usec would elapse between CS being enabled and CLK starting to toggle?  Also, why would another 12 usec elapse from the time transfer is complete (CLK stops to toggle) and CS is disabled?

I appreciate any help.

Regards,

Paul