Period is 20 times longer than expected in sample of ADC Periodic Framework

I got sample project of ADC Periodic Framework from Renersas. Imported it into E2, built and ran without problem. But the period was about 20 times longer then 10 ms as setting. Then I had changed the period value, the clock source of the GPT. But the period difference kept there, always about 20 times.

I am using SK-S7G2. SSP 1.30.  E2 5.4.0.023.

The sample file name is: an-r11an0115eu0101-synergy-adc-periodic-fw-mod-guide.zip